1. Field of the Invention
The present invention relates to overcurrent protection circuits and semiconductor apparatus and, particularly, to an overcurrent protection circuit and a semiconductor apparatus which protect an output device from an overcurrent.
2. Description of Related Art
Automobiles, home electric appliances and so on use a semiconductor apparatus called a power switch to control voltages and currents.
An automobile has an actuator which converts an electric signal into a mechanical motion for fuel control or transmission control. An output transistor of the power switch controls the on/off of the current flowing into the actuator. Switching the output transistor from the “off” state to the “on” state is called “turn-on”, and switching it from the “on” state or “turn-on” state to the “off” state is called “shut-down”. A metal oxide semiconductor field effect transistor, hereinafter as MOS, is used for the output transistor, for example.
In an automobile, a wire harness leading from an output terminal to a load such as an actuator can come off to touch a chassis or the like, which is called a load short-circuit. If the power switch mounted in an automobile starts the turn-on operation under the load short-circuit state, a large current flows into the output transistor while a battery voltage is applied between the transistor's drain and source, which results in breakdown of the output transistor due to heat. Further, if it is in an overcurrent state due to an abnormal load, a large current flows into the output transistor while a certain voltage is applied between its drain and source, which also results in breakdown of the output transistor due to heat. To prevent the breakdown of the output transistor due to the overcurrent, it is required to shut down the circuit or the output transistor instantaneously in the above cases. An overcurrent protection circuit is used for this purpose.
One example of the overcurrent protection circuit combines a timer circuit and a monitor circuit which monitors a voltage between the drain and source of an output transistor, which is disclosed in Japanese Patent No. 2882597 and illustrated in FIGS. 3 and 4. This overcurrent protection circuit shuts down the circuit if the drain-source voltage of the output transistor does not become lower after a given period of time.
Particularly, in the load short-circuit state which gives a stress (load) to the output transistor, it is necessary to shut down the circuit as soon as possible to reduce the stress on the output transistor. However, if the timer is set too short, it causes false anomaly detection to wrongly shut down the circuit in the normal load state. In order to protect the output transistor more safely, a timer circuit which can shut down the circuit immediately in the event of a short circuit in a load without false detection is required.
FIG. 7 is a circuit diagram of a conventional power switch. The power switch 700 includes an output transistor 704, an output voltage detection circuit 707, a timer circuit 750, and a control circuit 713. The timer circuit 750 has a constant current device 708, a Pch enhancement MOS (hereinafter as Pch MOS) 709, a Pch MOS 710, a capacitor 711, and an inverter 712.
The output transistor 704 is a switch for controlling the current and voltage output to a load 705, and it is, for example, an Nch MOS. The output transistor 704 has a drain connected to a first power supply 701, a gate connected to the output side of the control circuit 713, and a source connected to one side of the load 705 through an output terminal 706. The other side of the load 705 is connected to a third power supply 703.
The Pch MOS 709 and the Pch MOS 710 form a current mirror. The sources of the Pch MOS 709 and 710 are connected to the first power supply 701, and the gates are connected to each other and further connected to the drain of the Pch MOS 709. The drain of the Pch MOS 709 is connected to a second power supply 702 through the constant current device 708. The drain of the Pch MOS 710 is connected to the second power supply 702 through the capacitor 711 and also to the control circuit 713 through the inverter 712.
The inverter 712 receives voltages from the first power supply 701 and the second power supply 702. The inverter 712 has the input side connected to the drain of the Pch MOS 710, and the output side connected to the input side of the control circuit 713. The output voltage detection circuit 707 has the input side connected to the output terminal 706, and the output side connected to the input side of the control circuit 713.
The control circuit 713 receives in the input side the output signals from the inverter 712 and the output voltage detection circuit 707, and an input signal 740 from a microcomputer or the like. In accordance with these signals, the control circuit 713 outputs from the output side a gate signal of the output transistor 704 and a voltage of the second power supply 702.
In the power switch 700, the voltage of the second power supply 702 is the same as the voltage of the first power supply 701 before input of the input signal 740 from the microcomputer or the like. Upon input of the input signal 740, a voltage difference is created between the second power supply 702 and the first power supply 701 to activate the timer circuit 750. At the same time, the control circuit 713 outputs a gate signal to turn on the output transistor 704, thereby starting the turn-on of the output transistor 704.
When the timer circuit 750 operates, the current from the constant current device 708 which is reduced in the current mirror composed of the Pch MOS 709 and 710 is charged into the capacitor 711. If the capacitor 711 is charged to a certain voltage to reach the threshold of the inverter 712, the output of the inverter 712 is inverted. This time is a timer time t1.
The output voltage detection circuit 707 monitors the drain-source voltage of the output transistor 704. For example, if the output voltage detection circuit 707 is an inverter, the output of the output voltage detection circuit 707 is inverted when the voltage of the output terminal 706, hereinafter as an output voltage, reaches the threshold V1 of the inverter. The control circuit 713 receives the outputs from the inverter 712 and the output voltage detection circuit 707. If the output voltage does not reach V1 by the timer time t1, an anomaly is detected and the circuit is shut down.
FIGS. 8A, 8B, and 8C show examples of the output waveforms of the power switch 700. In the graphs of FIGS. 8A to 8C, a solid line (i) shows the turn-on of the output transistor when the load 705 is the normal state, a dashed line (j) shows the turn-on when the output terminal 706 is short-circuited to the third power supply 703, called the load short-circuit state. A double dashed line (k) shows the turn-on when an overcurrent occurs. The voltage detected by the output voltage detection circuit 707 is V1, and the timer value of the timer circuit 750 is t1. The crossing point of t1 and V1, which is P1(t1, V1), is an overcurrent detection reference, called a detection reference point.
FIG. 8A shows the output waveforms in the case where V1 is set high and t1 is set long. In the normal state shown in the line (i), the output voltage V reaches V1 at t1. Thus, the circuit is determined as normal and not shut down. In the overcurrent state shown in the line (k), the output voltage V does not reach V1 at t1. Thus, anomaly is correctly detected and the circuit is shut down for safe. However, in the load short-circuit state shown in the line (j), a large current flows immediately after the turn-on, and the large current cannot be detected until t1. Thus, excessive heat can break down the output transistor 704.
If, in the normal state shown in the line (i), the output voltage V falls below V1 after t1, the circuit is immediately shut down.
FIG. 8B shows the output waveforms in the case where t1 is set shorter than in FIG. 8A. In the load short-circuit state and the overcurrent state shown in the lines (j) and (k), the output voltage V does not reach V1 at t1; thus, anomaly is correctly detected to shut down the circuit. However, in this case, the output voltage V does not reach V1 at t1 in the normal state shown in the line (i) as well; thus, anomaly is wrongly detected to shut down the circuit.
FIG. 8C shows the output waveforms in the case where V1 is set smaller and t1 is set shorter than in FIG. 8A. In the normal state shown in the line (i), the output voltage V reaches V1 at t1; thus, the circuit is determined as normal and not shut down. In the load short-circuit state shown in the line (j), the output voltage V does not reach V1 at t1; thus, anomaly is correctly detected and the circuit is shut down. However, in the overcurrent state shown in the line (k), the output voltage V reaches V1 at t1; thus, anomaly cannot be detected and the circuit is not shut down. Excessive heat can thereby break down the output transistor 704.
As described above, use of a single detected output voltage and a single timer value causes false detection and incomplete detection, resulting in a low detection accuracy.
A protection circuit including two timers is disclosed in Japanese Unexamined Patent Application Publication No. 2002-33647 and illustrated in FIG. 3. This circuit detects overcurrent by monitoring a current with a sense MOS. The circuit has problems that it is necessary to place a sense MOS and it is difficult to change a detection threshold and a timer value.
The present invention has recognized that overcurrent protection circuits which set a single detection output voltage and a single timer value are subject to false detection and incomplete detection, having low detection accuracy. For example, as described above, the circuit cannot detect the load short-circuit state if a timer value is long. The circuit wrongly determines the normal state as an abnormal state if a timer value is short. Further, the circuit cannot detect the overcurrent state if a timer value is short and a detection voltage is low.